PCIe x4 connections to LS1021A

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PCIe x4 connections to LS1021A

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fzhang
Contributor II

Using LS1021A to communicate with FPGA (Arria V) through PCIe x4 bus. Is there a reference design or example for PCIe x4 connections to LS1021A? I am checking the reference manual.

Any responses are appreciated.

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alexander_yakov
NXP Employee
NXP Employee

We do not offer "reference schematics", but we offer schematics from our LS1021A-based development boards to use as reference. Please create a support case to online technical support and request LS1021A-based development board schematic with PCIe x4 slot.

How I could create a Service Request? 


Have a great day,
Alexander

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alexander_yakov
NXP Employee
NXP Employee

We do not offer "reference schematics", but we offer schematics from our LS1021A-based development boards to use as reference. Please create a support case to online technical support and request LS1021A-based development board schematic with PCIe x4 slot.

How I could create a Service Request? 


Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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fzhang
Contributor II

Thank you, Alex.

I submitted the request. That will save me a lot of time.

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fzhang
Contributor II

All the data lanes are pretty clear. But need help on those control, reset, and reference clock pins below:

Capture.PNG

Thank you!

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fzhang
Contributor II
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