We are designing an iMX6 Dual system using both parallel DISP Video Outputs.
In the "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015",
"Table 37-6. IPU1 External Signals" suggests that IPU1 can drive both the DISP0 outputs and the DISP1 outputs (on the EIM pads)
"Table 37-7. IPU2 External Signals" suggests that IPU2 can drive the DISP0 outputs only - not the DISP1 outputs.
In other words, both IPU's can drive DISP0; only IPU1 can drive DISP1.
Is this info correct?
It is not clear from the Reference Manual which 8 pads to use for the pixel CLK, HSYNC, VSYNC and Data Enable outputs on these DISP0 and DISP1 ports?
Are these 8 pads documented somewhere?