Re: Same FTM module used for Input capture and PWM output

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Re: Same FTM module used for Input capture and PWM output

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nitinverma
Contributor III
Dear Petr,
If I do not set CnSC[ICRST] bit on channel configured for Input Capture mode then Input Capture is not working as expected.
 
Following are my observations:
 
* I'm using FTM0 module Channel 5 PWM Output and Channel 6 for Input Capture.
 
* Scenario 1: FTM_C6SC[ICRST] = 0 (RESET)
 
-> Signal of 100Hz is given to Channel 6 for Input Capture.
 
CASE A:
-> PWM Output is generating 50Hz signal which is lesser than the frequency received for Input Capture.
-> Captured FTM counter values (10 Samples) for Channel 6 through Input Capture mode are:
   {2429, 8679, 4513, 347, 6598, 2432, 8682, 4516, 350, 6595}
-> For 100Hz signal captured, FTM counter value should be 6250. 
    It's capturing variable counts however I can see that the difference between first two samples (8679-2429 = 6250) is exact as desired.
    But differences between other consecutive samples are not as desired (6250 to be precise).
 
CASE B:
-> Now, PWM Output is generating 200Hz signal which is greater than the frequency received for Input Capture.
-> Captured FTM counter values (10 Samples) for Channel 6 through Input Capture mode are:
   {518, 518, 518, 518, 518, 518, 518, 518, 518, 518}
-> For 100Hz signal captured, FTM counter value should be 6250. After some time it's giving following values:
   {637, 637, 637, 637, 637, 637, 637, 637, 637, 637}
-> It's capturing constant values however not at all desired (6250 to be precise). Even counter values are increasing gradually (from 518 to 637).
 
* Scenario 2: FTM_C6SC[ICRST] = 1 (SET)
 
-> Signal of 100Hz is given to Channel 6 for Input Capture.
 
CASE A:
-> PWM Output is generating 50Hz signal which is lesser than the frequency received for Input Capture.
-> Captured FTM counter values (10 Samples) for Channel 6 through Input Capture mode are:
   {6250, 6250, 6250, 6250, 6250, 6250, 6250, 6250, 6250, 6250}
-> Captured FTM counter values are as desired but PWM Output is not as desired.
 
CASE B:
-> Now, PWM Output is generating 200Hz signal which is greater than the frequency received for Input Capture.
-> PWM Output is as expected but Input Capture is not as desired.
 
* Are these all observations are because of common counter available for entire FTM module ? Please review above findings and let me know whether it's a hardware limitation that one FTM module can not be used for PWM Output and Input Capture simultaneously. Looking forward for your response
BR,
Nitin verma
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PetrS
NXP TechSupport
NXP TechSupport

Hi Nitin,

If the input capture is used the captured value will be in the range of CTIN to MOD.

As those are used to define output PWM period you have to be sure the external signal can be properly detected.

 

In scenario 1 CASE A the overflow happens, but not sure how do you set CTIN and MOD.

In scenario 1 CASE B the result can be expected as higher PWM frequency is generated so FTM counter is set to CTIN before external edge appears.

 

In scenario2 CASE A the behavior is also correct as the FTM counter is reseted on input edge, thus also PWM output cannot be correct. For the CASE B the effect should be the same as previous CASE B.

 

So could you specify what is the FTM system clock, the FTM counter clock (selected by FTMn_SC[CLKS]) , counter prescaler and what is CTIN and MOD values?

 

Seems you will need to count FTM counter overflows to get correct results.

BR, Petr

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nitinverma
Contributor III
Dear Petr,
Below are the configuration detail you asked. 
FTM System Clock: System PLL clock (80 MHz)
FTM Counter Clock: System Clock (FTMn_SC[CLKS] = 01)
Counter Prescaler: 128 (FTMn_SC[PS] = 111)
Counter Initial Value (FTMn_CNTIN): 0x0000
Modulo (FTMn_MOD): 0xFFFF
Please suggest if any change is required.
Thanks.
BR,Nitin verma
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