I'm using a TRK-MPC5604P kit and I'm following the MPC5643L "PWM triggered measurement concept" tech note that has been posted in this forum, (I'm using the DMA code as provide). I've changed it to use dual conversion mode (both ADC0 & 1), and I'm getting data, using a PWM trigger of about 1.28ms for testing purposes. The system clock is 40MHz, so the ADC clock is 20MHz. This board has a potentiometer wired to Port E0, which I've configured as ADC1, channel5. I've tested this port assignment using the provided driver, "A2D_GetSingleCh_ADC1(ch)" and that works fine. When using the PWM-CTU-FIFO-DMA, the data values are appropriate, but their location in the array written to by DMA from the FIFO is odd. Specifically, the values that I'm seeing in FreeMaster indicate that the bit for ADC0 is indicated with a "1" and ADC1 is indicated by a "0". Also, I expect the result from ADC0 to be written first, before ADC1, since ADC0 conversion is faster, but I'm seeing the opposite. Seems like my interpretation of ADC1 and ADC0, or the documentation, is reversed.
The following screenshot from FreeMaster indicates that ADC_result, the first value in the result from the FIFO is ADC0? Channel 5, with a value of 0x3Fe, (I have the potentiometer maxed at 3.3V). I see alternativing ADC1, ADC0 in the results, (expected) and I can connect the pot to any port and see the appropriate value change, (if I wire the pot to port E7, then ADC_result tracks ADC_result. If ADC 0&1 were reversed, this is the ADC order that I would expect. So I'm just wondering why ADC0 & 1 appear reversed from what I expect?
a) ADC1 result appears first in the FIFO, insted of ADC0 which has a faster conversion time;
b) ADC1 is indicated by a zero in the ADC results (Ref Man. 25.4.3 ADC result), and ADC0 is show with a "1".
5 bits in the upper 16 bits indicate the ADC unit (1bit) and the channel number (4 bits).
Here's how I configired the CTU ADC command list (triggered off PWM VAL0).
// ADC1B, ADC0A, shift ch_b left one bit
CTU_0.CLR.R = 0x60A4; // 5, 4 dual, first
CTU_0.CLR.R = 0x20C8; // 6, 8
CTU_0.CLR.R = 0x20E9; // 7, 9
CTU_0.CLR.R = 0x21EA; // F, 10
CTU_0.CLR.R = 0x4000; //first, stop
CTU_0.TH1.B.THRESHOLD0 = 0x7; /* one less thatn # of FIFO 0 entries.*/
//------------------------------------------ADC channel initialization.
void ADC_Init (void)
ADC_0.MCR.R = 0; //MCR 0x8002-0000
ADC_0.MCR.B.OWREN = 1; //overwrite enable
ADC_0.MCR.B.CTUEN = 1; //CTU mode
ADC_0.NCMR.R = 0x00F0; //000-0111-1110-0000 enabled conversion channels
ADC_0.CTR.B.INPCMP = 2; //1.2us at 20Mhz
ADC_0.CTR.B.INPLATCH = 1;
ADC_0.CTR.B.INPSAMP = 13;
ADC_0.CTR.B.OFFSHIFT = 1; //tranisition at 1/2 LSB
ADC_1.MCR.R = 0; //MCR 0x8002-0000
ADC_1.MCR.B.OWREN = 1; //overwrite enable
ADC_1.MCR.B.CTUEN = 1; //CTU mode
ADC_1.NCMR.R = 0x80E0; //000-0111-1110-0000 enabled conversion channels
ADC_1.CTR.B.INPCMP = 0; //3us at 20MHz
ADC_1.CTR.B.INPLATCH = 1;
ADC_1.CTR.B.INPSAMP = 14;
ADC_1.CTR.B.OFFSHIFT = 1; //tranisition at 1/2 LSB