I start to implement vxWorks QSPI driver based on Freescale iMX6SX SABRE-SDB. But no response from flash chip.
Register setting about IOMUX:
1. IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B (20E_017Ch) = 2, Select signal QSPI2A_DATA0
2. IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B (20E_0174h) = 2, Select signal QSPI2A_DATA1
3. IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B (20E_0144h) = 2, Select signal QSPI2A_DATA2
4. IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B (20E_0148h) = 2, Select signal QSPI2A_DATA3
5. IOMUXC_SW_MUX_CTL_PAD_NAND_CLE (20E_014Ch) = 2, Select signal QSPI2A_SCLK
6. IOMUXC_SW_MUX_CTL_PAD_NAND_ALE (20E_0140h) = 2, Select signal QSPI2A_SS0_B
7. IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B (20E_04C4h) = 0x70a1
8. IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B (20E_04BCh) = 0x70a1
9. IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B (20E_048Ch)= 0x70a1
10. IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B (20E_0490h)= 0x70a1
11. IOMUXC_SW_PAD_CTL_PAD_NAND_CLE (20E_0494h)= 0x70a1
12. IOMUXC_SW_PAD_CTL_PAD_NAND_ALE (20E_0488h)= 0x70a1
Same settings for QSPI2B.
Register setting about QSPI clocks:
1. CCM_CS2CDR (20C_402Ch):
qspi2_clk_sel = 3, derive clock from PLL2 PFD2. PLL2 PFD2 is 396MHz.
qspi2_clk_pred = 1, divide by 2
qspi2_clk_podf = 0, divide by 1.
So QSPI2_CLK_ROOT is 396/2 = 198 MHz.
2. CCM_CCGR4 (20C_4078h):
CG5 = 3, qspi2 clock (qspi2_clk_enable)
Send "READ ID" (9Fh) command to flash chip, get all FFh data from flash. During reading, no clock signal is found on flash chip 'C' pin (measured on TP123 - QSPI2A_SCLK). After the command issue, QSPI interrupt generates, QSPI_FR = 8000001h.
What register save the value of QSPI_AMBA_BASE?
vxWorks QSPI driver works fine on Freescale vf610 tower board (TWR-VF65GS10). Porting it to iMX6sx, it can't work. Are there differences between their QSPI controllers? What is wrong? Can you send me QSPI driver sample code?