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Concurrent DDR writes from SDMA and AP Core

Question asked by Rolf Wöhrmann on Dec 26, 2016
Latest reply on Dec 27, 2016 by Rolf Wöhrmann

Hi

 

how are concurrent writes from SDMA FU Bursts and writes from A9 Core to non-cached memory  are arbitrated? Is it possible to give SDMA writes prio over A9 Core writes?

 

Thanks

Rolf

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