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In LS1043A, SERDES Clocking Query

Question asked by Logesh S on Dec 25, 2016
Latest reply on May 14, 2020 by Friedrich Seifert

In LS1043A, Please confirm the Clocking and Reset Sequence.

(Please correct if my understanding is wrong,)

Step 1: SYSCLK, DDRCLK needs to supplied before asserting PORESET is Asserted.

Step 2: After Desassertion of PORESET RCW data is loaded and HRESET is remain asserted.

Step 3: LS1043A PLLs (Platform, Core, other PLLs including SerDesPLL)begins to lock as per the setting in RCW data.

Step 4: HRESET is Deasserted.


My Actual doubt is does SerDes Reference clock(100MHz - PCIe and 100/156.25MHz- SGMII/XFI)  need to be provided at which step of above sequence? or We shall provide SerDes Reference clock after deassertion of HRESET(STEP4)?