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MPC8306 256MB DDR2 connection in MPC8306 SOM

Question asked by joy dong on Dec 21, 2016
Latest reply on Jan 2, 2017 by joy dong

  We are developing a processor board with the MPC8306. We want to use the DDR2 controller to connect the MPC8306 with a 256MB DDR2 Memory (MT47H128M16 from Micron).

 

  In the original design, the MPC8306 som uses the MT47H64M16( MT47H64M16 is 128MiB DDR2), and it configured in the MPC8306SOM.h as follows:

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE                   0x00000000    /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE    CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDRCDR                       0x73000002    /* DDR II voltage is 1.8V */
#define CONFIG_SYS_DDR_SIZE                     128    /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG     0x80844102    
#define CONFIG_SYS_DDR_CLK_CNTL          DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05          /* 0x02000000 */
#define CONFIG_SYS_DDR_MODE        ( ( 0x440C << SDRAM_MODE_ESD_SHIFT ) \
                                                                  | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )                        /* 0x440C0232 */
#define CONFIG_SYS_DDR_MODE2        0x8000c000
#define CONFIG_SYS_DDR_INTERVAL    ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
                                                                    | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )         /* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS     0x00000007
#define CONFIG_SYS_DDR_SDRAM_CFG    0x43100000    
#define CONFIG_SYS_DDR_SDRAM_CFG2   0x60401000

 

  In our design, we uses the MT47H128M16, and it configured in the MPC8306SOM.h as follows:

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE                   0x00000000    /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE    CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDRCDR                       0x73000002    /* DDR II voltage is 1.8V */
#define CONFIG_SYS_DDR_SIZE                     256    /* 256MB */
#define CONFIG_SYS_DDR_CS0_CONFIG     0x80844202    /* 3 logical bank bits, 14 row bits, 10 column bits */
#define CONFIG_SYS_DDR_CLK_CNTL          DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05          /* 0x02000000 */
#define CONFIG_SYS_DDR_MODE        ( ( 0x440C << SDRAM_MODE_ESD_SHIFT ) \
                                                                  | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )                        /* 0x440C0232 */
#define CONFIG_SYS_DDR_MODE2        0x8000c000
#define CONFIG_SYS_DDR_INTERVAL    ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
                                                                    | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )         /* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS     0x0000000f  /* 256MB */
#define CONFIG_SYS_DDR_SDRAM_CFG    0x43100000    
#define CONFIG_SYS_DDR_SDRAM_CFG2   0x60401000

 

  when u-boot start run, it crashed after show the text “DRAM: 256 MiB”

 

    But, when we change #define CONFIG_SYS_DDR_SIZE   128    /* 256MB */,then it's okay。

 

  Our board can not use 128 ~ 256 M of the MT47H128M16, does anybody know how to solve this problem?

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