Our customer has question below.
Problems are occurring with combination of i.MX 6Q and PF 0100.
In the Schematic checking page of the HW Design Checking List, there is the following statement in the line 18 of "Power and Decouple".
PF0100 default configuration power up sequence can not meet i.MX6 requirement. When using default configuration, please add an external reset IC. SABRE AI reference design can be a reference.
Which specifications do not match? Is it necessary to connect the reset IC externally with the combination of i.MX6 and PF0100?
What is the correct answer to restart the reset in milliseconds after PORB VDD_ARM_CAP starts up?