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LS1021 SPI reception with eDMA

Question asked by Pratap Gaikwad on Dec 20, 2016
Latest reply on Dec 23, 2016 by Pratap Gaikwad

I am trying to use SPI with eDMA. The SPI transmission with eDMA is working properly, but I am facing issue with SPI reception with eDMA. Please see below details on issue:

 

eDMA is not able to transfer content from SPI RX FIFO to destination RAM location properly. After the trigger from SPI RX FIFO Drain event, DMA transaction gets completed but SPI RX FIFO pointer does not change regularly after each DMA read operation on SPI POPR register

 

Following configuration is used:

  1. SPI Configuration for RX DMA transfer: 
    • Enable RX FIFO Drain DMA triggering in RSER register.
  2. eDMA channel configuration:
    • Source Port Size: 32 bit
    • Major loop count: Total number of 32bit-words to be transferred
    • Source Address: Address of SPI POPR register
    • Destination offset: 4 
    • Source offset: 0
    • Destination Address: Address of RAM buffer
    • NBYTES (Minor loop): 4 bytes
    • Destination port Size: 32 bit
    • Used DMA channel number: 1
  3. DMA MUX configuration
    • Channel 1 Trigger source -> SPI RFDF

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