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TWR-KV58F220M flash problem

Question asked by Michael Ellis on Dec 19, 2016
Latest reply on Dec 21, 2016 by Alice_Yang

I have a TWR-KV58F220M board and I'm working on flash update routines.

 

If I use the default BOARD_BootClockRUN() routine at startup I am able to run the pflash demo code with no problems.  If I use a customized BOARD_BootClockHSRUN() routine I get a kStatus_FLASH_AccessError when I attempt to erase a flash sector.  The two clock initialization routines are shown below.  In both cases my bus/flash clock should be running at 25 MHz.  Any thoughts?

 

void BOARD_BootClockRUN(void)
{
   /*
   * Core clock: 150MHz
   */

 

   // PLL: MCGOUTCLK = OSCCLK * (VDIV+16)/(2*(PRDIV+1))
   // = 50 MHz * (8+16)/(2*(3+1))
   // = 50 MHz * 24/8
   // = 150 MHz
   const mcg_pll_config_t pll0Config = {
      .enableMode = 0U,
      .prdiv = 3U,
      .vdiv = 8U,
   };

 

   // SIM: CLKn = MCGCLK / (OUTCLKn+1)
   // system clock = 150 MHz / (0 + 1) = 150 MHz
   // Fast Peripheral clock = 150 MHz / (1 + 1) = 75 MHz
   // Flexbus clock = 150 MHz / (1 + 1) = 75MHz
   // Bus/Flash clock = 150 MHz / (5 + 1) = 25 MHz
   const sim_clock_config_t simConfig = {
      .pllFllSel = 1U,                     /* PLLFLLSEL select PLL */
      .er32kSrc = 3U,                  /* ERCLK32K selection, use LPO. */
      .clkdiv1 = 0x01150000U,   /* SIM_CLKDIV1: OUTDIV1 = 0, OUTDIV2 = 1, OUTDIV3 = 1, OUTDIV4 = 5 */
   };

 

   CLOCK_SetSimSafeDivs();
   BOARD_InitOsc0();

   CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);

   CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
   CLOCK_SetSimConfig(&simConfig);

   SystemCoreClock = 150000000U;
}

 

 

void BOARD_BootClockHSRUN(void)
{
/*
* Core clock: 200MHz
*/

 

SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}

CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();

 

// PLL: MCGOUTCLK = OSCCLK * (VDIV+16)/(2*(PRDIV+1))
// = 50 MHz * (24+16)/(2*(4+1))
// = 50 MHz * 40/10
// = 200 MHz
   const mcg_pll_config_t pll0Config = {
      .enableMode = 0U,
      .prdiv = 4U,
      .vdiv = 24U,
   };

 

   // SIM: CLKn = MCGCLK / (OUTCLKn+1)
   // system clock = 200 MHz / (0 + 1) = 200 MHz
   // Fast Peripheral clock = 200 MHz / (1 + 1) = 100 MHz
   // Flexbus clock = 200 MHz / (2 + 1) = 66.67 MHz
   // Bus/Flash clock = 200 MHz / (7 + 1) = 25 MHz
   const sim_clock_config_t simConfig = {
      .pllFllSel = 1U,                     /* PLLFLLSEL select PLL */
      .er32kSrc = 3U,                  /* ERCLK32K selection, use LPO. */
      .clkdiv1 = 0x01270000U,   /* SIM_CLKDIV1: OUTDIV1 = 0, OUTDIV2 = 1, OUTDIV3 = 2, OUTDIV4 = 7 */
   };

 

   CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);

   CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
   CLOCK_SetSimConfig(&simConfig);
   SystemCoreClock = 200000000U;
}

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