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Issue in Configuring PLL4 frequency

Question asked by femy varghese on Dec 19, 2016
Latest reply on Dec 19, 2016 by igorpadykov
We want to interface an audio codec to imx6dl processor. We are using PLL4 for SSI2. We are getting a value 147.456 MHz for PLL4 in the clock summary.
However, the PLL4 frequency range is 650MHz to 1.3GHz as per the datasheet. 
 While debugging we found that in the function clk_pllv3_av_set_rate() (), (ref:arch/arm/mach-imx/clk-pllv3.c), the value written to the register CCM_ANALOG_PLL_AUDIO(0x70) is 0x1029. This means the DIV_SELECT has a value of 0x29. 
However, when we read this back immediately after writing,  we are getting a value 0x1006. (ie DIV_SELECT is 0x06).
Please help us understand why the register is not changing after writing the required value? It looks like it is not changing from 0x06 which is the default value on reset.