We have two processors that are connected directly by a PCIe x1 Gen 1.1 link. The Root Complex (RC) is a P1011 and the EndPoint (EP) is a T1040. We have some software that configures the SoC including the PCIe bus and is trying to talk over the PCIe bus with limited success. The software is simple software that has a pointer into the other processor’s RAM and we try to read and write the first address in the outbound window. For configuration we configure the an entry in the TLB1 to map the effective address to a physical address, A LAW register to route the physical address to one of the PEX controllers and then we configure the PEX controller with one inbound window and one outbound window. These windows are for memory transactions.
The RC is able to read and write the EP’s RAM but the EP is not able to either read or write the RC’s RAM. In the current version we have removed the code in the EP that tries to read from the RC’s RAM so it is only trying to write. The software on the EP is in an infinite loop that prints a dot to the serial port after every write then waits for 1 second. The symptom we see is that the EP executes this loop twelve times and then on the thirteenth write the CPU locks up. When it locks up the JTAG unit we have can’t even halt it. What are the likely things that could cause this behavior? Where should we start looking for mis-configuration? Could this be some type of connection problem (the links do train and we can complete writes and reads from the RC to the EP)? I noticed that the T1040RM states that the PEX can support 12 outstanding platform writes. Any connection to the number of writes before the lock up?
NOTE: We have a similar system with similar configuration with similar results except that the EP does not lock up unless we power off the RC.