Can the ASRC block handle input/output clock skew?

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Can the ASRC block handle input/output clock skew?

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dannysmith
Contributor II

Hi everyone

Looking into using the Asynchronous Sample Rate Converter (ASRC) in the i.MX 6 family for various audio related purposes. While reading the data sheet I found this note on available features:

Automatic accommodation to slow variations in the incoming and outgoing sampling rates.

How does this feature work? Could I set incoming and outgoing clocks to 48KHz and the ASRC block would take care of the clock skew present between these clocks (for instance, one of the clocks is running slightly faster or slower than the other)?

Regards,

Danny

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igorpadykov
NXP Employee
NXP Employee

Hi Danny

ASRC internally is a micro-coded FSM, so there is always delay between input and output clocks.

A bit more detailed description of its work can be found in its early version description in

http://www.nxp.com/assets/documents/data/en/reference-manuals/DSP56720RM.pdf

Best regards
igor
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dannysmith
Contributor II

Thank you for the info! I have read through the documentation but are still not sure of how the ASRC handles small variations in the input/output clocks.

Lets say we have a very accurate 48KHz input clock and a less accurate output clock running at 48003Hz. What will the ASRC do in this case? upsample to 48003Hz? If so, are there any limitations to this functionality?

If the clocks are both running at precise 48KHz, will the ASRC keep them in sync?

Best regards,

Danny