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i.MX6 broken up DDR byte lane swapping

Question asked by Henrik Foss on Dec 14, 2016
Latest reply on Dec 14, 2016 by igorpadykov


According to "Routing considerations" in the hardware development guide to i.MX6 says it supports complete byte lane swapping. Does this also apply to broken up DDR byte lane swapping, as shown underneath:


Also the note in this subsection mentions that "target DDR IC register read value must be
transposed according to the data line swapping", can someone elaborate on the meaning of this?