We have our own drivers for the IPU and currently we support video using channel 23 on i.MX6Q and i.MXQP.
We recently tried to add the pre/prg initialization similar to the mxc drivers in Linux.
After correctly setting up the IPU, pre and prg blocks we end up with garbage being read and shown through the display interface. It never changes, and no matter what address we point the PRE to, the garbage looks the same.
We do however notice one bit is not being cleared in the pre engine. Note we are just trying single buffer mode for now.
In register HW_PRE_CTRL bit 4 SDW_UPDATE we notice after setting it the hardware store engine never seems to clear the bit.
"Indicates that the shadow register should be updated. If have any control register bits are changed,
Software have to set this bit, and then all register bits will be updated to shadow register end of current
frame in store engine. And then it will be cleared automatically by hardware."
Can you point us in the right direction as to what might be happening, that the bit is not being cleared? We are using IPU 1 so PRE0 and PRG0. We know the IDMAC and IPU configuration works without using PRE just fine. The only thing that we had to change for IDMAC setup was the address of the buffer to read. It needs to point to OCRAM2 address.
Also note we would like this to run without interrupts. For single buffer mode we want to setup pre/prg once and simply update data within the buffer. In double buffer mode we would like to set the next buffer in pre to be taken on v-sync. But for now single buffer is a start.
Here is a dump of our setup registers:
We appreciate any help to indicate why that shadow update bit is not getting ingested. We suspect something wrong in the store or prg setup, but its not clear. We also supect this is why the engines aren't starting up and reading data and placing it in OCRAM.