Yocto / buildroot 1280x480 lvds display flicker

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Yocto / buildroot 1280x480 lvds display flicker

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imxauto
Contributor II

I am trying to use an iMX6 Sabrelite with 1280x480 lvds display.

its a Sharp Display LQ123K1LG03 with Frequency   1/Tc 40 53.172 56 MHz

The board boots up fine.

I have tried with both latest buildroot and Yocto (kernel 4.1.15) but no matter what clock /frequency I set in file imx6qdl-sabrelite.dtsi, there is a flicker on the screen.

Here is a snapshot

lvds-channel@0 {
          crtc = "ipu1-di1";
          fsl,data-mapping = "jeida";
          fsl,data-width = <24>;
          status = "okay";
          primary;

          display-timings {
               t_lvds: t_lvds_default {
                    /* lg1280x800 values may be changed in bootscript */
                    clock-frequency = <53172000>;
                    hactive = <1280>;
                    vactive = <480>;
                    hback-porch = <0>;
                    hfront-porch = <398>;
                    vback-porch = <0>;
                    vfront-porch = <35>;
                    hsync-len = <10>;
                    vsync-len = <10>;
               };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Any Idea what could be the issue?

Labels (3)
9 Replies

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gary_bisson
Senior Contributor III

Hi,

Are you sure U-Boot doesn't override your clock setting? As the comment says our display configuration is done via U-Boot and those values can be overwritten.

Display configuration from U-Boot - Boundary Devices 

Also, are the other values (back/front porch) matching your display?

Regards,

Gary

1,778 Views
imxauto
Contributor II

I tried setting those display timings through boot arguments .

Apparently its set what we want it to be. 

the entire boot environment is attached as text.

cmd_lvds=fdt set fb_lvds status okay;fdt set fb_lvds interface_pix_fmt RGB24;fdt set ldb/lvds-channel@0 fsl,data-width <24>;fdt set ldb/lvds-c;

fb_lvds=LQ123K1LG03:24:53172000,1280,480,353,47,39,4,8,2

About back/front porch I read somewhere that they only move the screen and have no/minimal role in display flicker.

This is the timing I found i datasheet of the display

ParameterSymbolMin.Typ.Max.UnitRemark
Frequency1/Tc4053.17256MHz
Horizontal periodTH142016881895clock
25.431.74647.4μs
Horizontal period (High)THd128012801280clock
Vertical periodTV487525575line
-16.7-msNote1
Vertical period (High)TVd480480480line

[Note1]   In case of lower frequency, the deterioration of display quality, flicker etc.,may be occurred.

Is something, somewhere else overriding the settings?

I have similar results with buildroot and Yocto.

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gary_bisson
Senior Contributor III

Hi,

Your 'cmd_lvds' looks wrong. It should be something like:

cmd_lvds=fdt set fb_lvds status okay;fdt set fb_lvds interface_pix_fmt RGB24;fdt set ldb/lvds-channel@0 fsl,data-width 
<24>;fdt set ldb/lvds-channel@0 fsl,data-mapping spwg;fdt set t_lvds clock-frequency <68152388>;fdt set t_lvds hactive 
<1280>;fdt set t_lvds vactive <800>;fdt set t_lvds hback-porch <5>;fdt set t_lvds hfront-porch <63>;fdt set t_lvds vbac
k-porch <2>;fdt set t_lvds vfront-porch <39>;fdt set t_lvds hsync-len <1>;fdt set t_lvds vsync-len <1>;

Have you properly rebooted once you have set fb_lvds and saved the environment?

Maybe your terminal app (minicom?) doesn't wrap the lines that exceed the size of the screen (check wrap option).

If you want to check the clock once booted up, you can have a look at the debugfs as follows:

# cat /sys/kernel/debug/clk/clk_summary | grep ldb

Does it match the frequency you asked for?

Regards,

Gary

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imxauto
Contributor II

Hi Gary,

Thanks for the reply,

Based on above, I created a new fbpanel entry with

                .pixclock       = 1000000000000ULL/((1688)*(525)*60),\

Which is displayed on terminal as 

lvds: lq123k1lg03:18x2,38:53174518,1280,480,132,132,31,11,144,3

Yes, we are using minicom and here is the complete output for cmd_lvds

cmd_lvds=fdt set fb_lvds status okay;fdt set fb_lvds interface_pix_fmt RGB666;fdt set ldb/lvds-channel@0 fsl,data-width <18>;fdt set ldb/lvds-c
hannel@0 fsl,data-mapping spwg;fdt set t_lvds clock-frequency <53174518>;fdt set t_lvds hactive <1280>;fdt set t_lvds vactive <480>;fdt set t_l
vds hback-porch <132>;fdt set t_lvds hfront-porch <132>;fdt set t_lvds vback-porch <31>;fdt set t_lvds vfront-porch <11>;fdt set t_lvds hsync-l
en <144>;fdt set t_lvds vsync-len <3>;

and here is the clock output.

It does not match what we are trying to configure (53172000) possibly due to rounding off.

cat /sys/kernel/debug/clk/clk_summary | grep ldb output

                      ldb_di1_sel           0            0   372221626          0 0  
                         ldb_di1_div_7           0            0    53174518          0 0  
                            ldb_di1_div_sel           0            0    53174518          0 0  
                               ldb_di1           0            0    53174518          0 0  
                         ldb_di1_div_3_5           0            0   106349036          0 0  
                   ldb_di0_sel            1            1   365538461          0 0  
                      ldb_di0_div_7           1            1    52219780          0 0  
                         ldb_di0_div_sel           1            1    52219780          0 0  
                            ldb_di0           1            1    52219780          0 0  
                      ldb_di0_div_3_5           0            0   104439560          0 0 
‍‍‍‍‍‍‍‍‍‍‍‍

I tried with a lower frequency and it almost always skips 53172000.

could this be impacting the display?

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gary_bisson
Senior Contributor III

Hi,

I don't think the frequency difference is that big. However I would try with a higher frequency (not lower). As you can see on the clock tree, the ldb_di1 frequency is 53174518 which should be better.

Regards,

Gary

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imxauto
Contributor II

Hi,

I've been trying many other frequencies mostly without any success.

But with this one

setenv fb_lvds LQ123K1LG03:18:55412100,1280,480,9,590,5,85,16,5

the flicker is noticeably less but still present.

the boot prints and fbset output does not tell me anything specific.

mxc_sdc_fb fb@0: 1280x480 h_sync,r,l: 16,590,9  v_sync,l,u: 5,85,5 pixclock=55413000 Hz
imx-ipuv3 2400000.ipu: use special clk parent
imx-ipuv3 2400000.ipu: disp=1, pixel_clk=55413000 54308571 parent=54308571 div=1

#fbset

mode "1280x480-51"
    # D: 55.414 MHz, H: 29.242 kHz, V: 50.856 Hz
    geometry 1280 480 1280 512 32
    timings 18046 9 590 5 85 16 5
    rgba 8/16,8/8,8/0,8/24
endmode

 

So now I have following questions:

How to calculate kernel parameters from datasheet timings?

Does flicker has anything to do with vertical refresh rate?

Why changing parameters via fbset does not work / have no impact on display?

In all the articles that I read, I found that using Typ. frequency almost always works, but this is not the case with this one. I dont think this should be hit and try as there are so many custom displays in the market working just fine.

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gary_bisson
Senior Contributor III

Hi,

I guess your option now is to contact the display manufacturer to have more details about the timings. Every display datasheet I've seen was more detailed than this.

In your case you only have the period and guessed the back/front porch + length.

Also, it happened in the past that we had to tweak the values since the typical one were not satisfying.

Regards,

Gary

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imxauto
Contributor II

Hi Gary,

I did not get any reply from SHARP so have just one more question for you.

When we boot, till the time its u-boot display there's no flicker, as soon as the kernel takes over, a thick gray line starts to roll over it.

Any idea?

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gary_bisson
Senior Contributor III

Hi,

Once again I suggest looking at the clock tree. The display clocks are completely different between U-Boot and the kernel.

Unfortunately there's no easy way (that I know of) to display the clock tree from U-Boot you I guess you'll have to read the source code and dump a few registers to know which parent is used and what frequency is selected for the display.

Regards,

Gary

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