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CSI-2 60 fps issue

Question asked by John Dusing on Dec 13, 2016
Latest reply on Dec 15, 2016 by John Dusing

CSI-2 i.MX6Q question.  what is the register and bit I need to watch to determine when CSI-2 end of frame packets are received through the interface?  Is the source code for debug "ipu_common.c" and is the "IPU_INT_STAT" the right register?  Debug higher up indicates 33fps, and the data stream on the input to the CPU says 60fps.  Trying to determine why I am only getting half the frames.

 

Thanks for you input!

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