CSI-2 i.MX6Q question. what is the register and bit I need to watch to determine when CSI-2 end of frame packets are received through the interface? Is the source code for debug "ipu_common.c" and is the "IPU_INT_STAT" the right register? Debug higher up indicates 33fps, and the data stream on the input to the CPU says 60fps. Trying to determine why I am only getting half the frames.
Thanks for you input!