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9S08AC60 Reset Levels

Question asked by Michael Fugere on Dec 9, 2016

In my end-user application/product, I need the ability for a "master" MC9S08AC60CPUE to be able to reset a "slave" MC9S08AC60CPUE , while still allowing for pod debug & production programming of the "slave" regardless of the state of the master.  To do this inexpensively, I am using a series resistor from a Master's I/O pin to the slave's reset pin, and slave's reset pin is also connected to the debug pod connector on the PCB.  The reset pin on the slave presently has no externally added pullup, but does have 100nF filter cap to GND.  The internal pullup on the reset pin appears to be approximately 30K, as with a series resistance of 5K to the Master's I/O pin, it can only maintain a low voltage of 0.7V, which I think may not be reliably resetting the slave.   If I lower series resistance to 2.7K, it can maintain a low level of approximately 0.38V.

The MC9S08AC60 datasheet indicates a maximum low voltage input level of 0.35xVdd which would yield  1.75V in my application, but I think the reset line must go significantly lower than that to ensure reset.  I don't want to go too low in series resistance and then have problems with the programming pod current limit.

 

So, what levels of voltage are necessary on the dedicated Reset Pin to ensure the micro is held in reset state?

 

Thank you

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