AnsweredAssumed Answered

Core halt and reset problem at MPC5777C

Question asked by JONGMIN NA on Dec 8, 2016
Latest reply on Dec 12, 2016 by Peter Vlna

Hello Everyone~!

 

I have a problem with MPC5777C.

First of all, My System specification is

- MCU : MPC5777C with MCAL RTM Version

- AUTOSAR OS : ETAS RTA-OS

- Debugger : Trace32

 

 

I configured OS for using dual core. each cores assigned PIT2(for Core 0) and PIT3(for Core 1) for OS tick base.

My Core Dsiable function is like this,

 switch(DisableCPUID)
 {
 case 0:
      SIU.HLT1.B.CORE0 = 1; 
      asm("wait");
      SIU.RSTVEC0.R = (unsigned long)&_start | 0x2;
      break;
 case 1:
      SIU.HLT1.B.CORE1 = 1; 
      asm("wait");
      SIU.RSTVEC1.R = (unsigned long)&os_example_init_core | 0x3;
      break;
 default:
      break;
 }

 

If Core 1 call this function, FCCU detect CMU_COMP error.

But Even though FCCU error is invoked, Core 0 is running well and Core 1 is halted.

 

Can you let me know this reason? Why CMU_COMP error is inovked?

 

Best Regards,

JM

Outcomes