AnsweredAssumed Answered

i.MX31 board unstable

Question asked by Michael Thalmeier on Dec 5, 2016
Latest reply on Dec 27, 2016 by Victor Linnik

Hi !

We have a custom i.MX31 based board that has frequent lockups where the processor seems to come to a halt.
This halting of all processing can be viewed in u-boot (2012.04-rc1) as well as in a running linux system (kernel 3.0).

I have now attached a JTAG debugger with the following outcome:

When the board is seemingly halted the CPU is still running (according to the JTAG debugger) and I need to halt it manually to inspect all registers/memory.

 

Does anyone have an idea on what is going on here or how to investigate this further?

 

iMX31>halt

CORE0 -> Arm1136 - stopped by user request (ARM)
PC=0x1FFFFFD0, CPSR=0x600001DB

 

iMX31> info registers

Core 0: Arm1136
r0 : 00000000
r1 : 80771F8C
r2 : 00000000
r3 : 00000000
r4 : 00000000
r5 : FFFFFFFF
r6 : 80771F8C
r7 : 00000000
r8 : 8F515F64
r9 : 00000000
r10 : 0000044A
r11 : 81100000
r12 : FFE635F8
sp : 000211C6
lr : 20000004
pc : 1FFFFFD8
cpsr : 600001D7
spsr : 600001D7
State: Abort


iMX31> info cp14

Core 0: Arm1136
didr -> Debug ID Register (ro) (0x1000) = 0x15110004
dscr -> Debug Status & Control Register (rw) (0x1100) = 0x00006A03
dtr -> Data Transfer Register (rw) (0x1500) = 0x00000007
vcr -> Vector Catch Register (rw) (0x1700) = 0x00000000
bvr0 -> Breakpoint Value Register 0 (rw) (0x9000) = 0xB6A73D18
bvr1 -> Breakpoint Value Register 1 (rw) (0x9100) = 0x922B7A1C
bvr2 -> Breakpoint Value Register 2 (rw) (0x9200) = 0x668A3D54
bvr3 -> Breakpoint Value Register 3 (rw) (0x9300) = 0xD6D0BCA8
bvr4 -> Breakpoint Value Register 4 (rw) (0x9400) = 0x24213FC5
bvr5 -> Breakpoint Value Register 5 (rw) (0x9500) = 0x5C47A4E5
bcr0 -> Breakpoint Control Register 0 (rw) (0xB000) = 0x00000000
bcr1 -> Breakpoint Control Register 1 (rw) (0xB100) = 0x00000000
bcr2 -> Breakpoint Control Register 2 (rw) (0xB200) = 0x00000000
bcr3 -> Breakpoint Control Register 3 (rw) (0xB300) = 0x00000000
bcr4 -> Breakpoint Control Register 4 (rw) (0xB400) = 0x00000000
bcr5 -> Breakpoint Control Register 5 (rw) (0xB500) = 0x00000000
wvr0 -> Watchpoint Value Register 0 (rw) (0xD000) = 0x256D1380
wvr1 -> Watchpoint Value Register 1 (rw) (0xD100) = 0xC0020D28
wcr0 -> Watchpoint Control Register 0 (rw) (0xF000) = 0x00000000
wcr1 -> Watchpoint Control Register 1 (rw) (0xF100) = 0x00000000

iMX31> info cp15

Core 0: Arm1136
id -> Main ID (ro) (0x1000) = 0x4107B364
cachetype -> Cache Type (ro) (0x3000) = 0x1D152152
tcmstatus -> TCM Status (ro) (0x5000) = 0x00010001
tlbtype -> TLB Type (ro) (0x7000) = 0x00000800
cpuf0 -> Processor Feature 0 (ro) (0x1100) = 0x00000800
cpuf1 -> Processor Feature 1 (ro) (0x3100) = 0x00000800
debf0 -> Debug Feature 0 (ro) (0x5100) = 0x00000800
auxf0 -> Auxiliary Feature 0 (ro) (0x7100) = 0x00000800
mmf0 -> Memory Model Feature 0 (ro) (0x9100) = 0x00000800
mmf1 -> Memory Model Feature 1 (ro) (0xB100) = 0x00000800
mmf2 -> Memory Model Feature 2 (ro) (0xD100) = 0x00000800
mmf3 -> Memory Model Feature 3 (ro) (0xF100) = 0x00000800
iattr0 -> Instr. Set Attributes 0 (ro) (0x1200) = 0x00000800
iattr1 -> Instr. Set Attributes 1 (ro) (0x3200) = 0x00000800
iattr2 -> Instr. Set Attributes 2 (ro) (0x5200) = 0x00000800
iattr3 -> Instr. Set Attributes 3 (ro) (0x7200) = 0x00000800
iattr4 -> Instr. Set Attributes 4 (ro) (0x9200) = 0x00000800
iattr5 -> Instr. Set Attributes 5 (ro) (0xB200) = 0x00000800
control -> Control (rw) (0x1001) = 0x0005107A
auxcon -> Auxiliary Control (rw) (0x3001) = 0x00000007
cpacon -> Coprocessor Access Control (rw) (0x5001) = 0x00000000
ttb0 -> Translation Table Base 0 (rw) (0x1002) = 0x00000000
ttb1 -> Translation Table Base 1 (rw) (0x3002) = 0x00000000
ttbcon -> Translation Table Base Control (rw) (0x5002) = 0x00000000
dac -> Domain Access Control (rw) (0x1003) = 0xFFFFFFFF
dfs -> Data Fault Status (rw) (0x1005) = 0x00000000
ifs -> Instr. Fault Status (rw) (0x3005) = 0x00000008
dfa -> Data Fault Address (rw) (0x1006) = 0x00000000
wfa -> Watchpoint Fault Address (rw) (0x3006) = 0x00000000
wfi -> Wait For Interrupt (wo) (0x9007) - write only
ieic -> Inv. Entire Instr. Cache (wo) (0x1507) - write only
iicmva -> Inv. Instr. Cache using MVA (wo) (0x3507) - write only
iicmsw -> Inv. Instr. Cache using Set/Way (wo) (0x5507) - write only
fpb -> Flush Prefetch Buffer (wo) (0x9507) - write only
febtc -> Flush Entire Branch Target Cache (wo) (0xD507) - write only
fbtce -> Flush Branch Target Cache Entry (wo) (0xF507) - write only
iedc -> Inv. Entire Data Cache (wo) (0x1607) - write only
idclmva -> Inv. Data Cache Line using MVA (wo) (0x3607) - write only
idclsw -> Inv. Data Cache Line using Set/Way (wo) (0x5607) - write only
ibc -> Inv. Both Caches (wo) (0x1707) - write only
cedc -> Clean Entire Data Cache (wo) (0x1A07) - write only
cdclmva -> Clean Data Cache Line using MVA (wo) (0x3A07) - write only
cdclsw -> Clean Data Cache Line using Set/Way (wo) (0x5A07) - write only
dsb -> Data Synchronization Barrier (wo) (0x9A07) - write only
dmb -> Data Memory Barrier (wo) (0xBA07) - write only
rcdsr -> Read Cache Dirty Status Register (ro) (0xDA07) = 0x00000000
rbtsr -> Read Block Transfer Status Register (ro) (0x9C07) = 0x00000000
spr -> Stop Prefetch Range (wo) (0xBC07) - write only
picl -> Prefetch Instr. Cache Line (wo) (0x3D07) - write only
ciedc -> Clean & Inv. Entire Data Cache (wo) (0x1E07) - write only
cidclmva -> Clean & Inv. Data Cache Line MVA (wo) (0x3E07) - write only
cidclsw -> Clean & Inv. Data Cache Line Set/Way (wo) (0x5E07) - write only
iitlb -> Inv. Instr. TLB (wo) (0x1508) - write only
iitlbse -> Inv. Instr. TLB Single Entry (wo) (0x3508) - write only
iitlbasid -> Inv. Instr. TLB Entry on ASID match (wo) (0x5508) - write only
idtlb -> Inv. Data TLB (wo) (0x1608) - write only
idtlbse -> Inv. Data TLB Single Entry (wo) (0x3608) - write only
idtlbasid -> Inv. Data TLB Entry on ASID match (wo) (0x5608) - write only
iutlb -> Inv. Unified TLB (wo) (0x1708) - write only
iutlbse -> Inv. Unified TLB Single Entry (wo) (0x3708) - write only
iutlbasid -> Inv. Unified TLB Entry on ASID match (wo) (0x5708) - write only
dcl -> Data Cache Lockdown (rw) (0x1009) = 0xFFFFFFF0
icl -> Instr. Cache Lockdown (rw) (0x3009) = 0xFFFFFFF0
dtcmr -> Data TCM Region (rw) (0x1109) = 0x00000000
itcmr -> Instr. TCM Region (rw) (0x3109) = 0x00000000
tlbl -> TLB Lockdown (rw) (0x100A) = 0x00000000
prr -> Primary Region Remap (rw) (0x120A) = 0x00000000
nmr -> Normal Memory Remap (rw) (0x320A) = 0x00000000
dmaisp -> DMA Ident. & Stat. Present (ro) (0x100B) = 0x00000000
dmaisq -> DMA Ident. & Stat. Queued (ro) (0x300B) = 0x00000000
dmaisr -> DMA Ident. & Stat. Running (ro) (0x500B) = 0x00000000
dmaisi -> DMA Ident. & Stat. Interrupting (ro) (0x700B) = 0x00000000
dmaua -> DMA User Accessibility (rw) (0x110B) = 0x00000000
dmacn -> DMA Channel Number (rw) (0x120B) = 0x00000000
dmaes -> DMA Enable (Stop) (wo) (0x130B) - write only
dmaep -> DMA Enable (Start) (wo) (0x330B) - write only
dmaec -> DMA Enable (Clear) (wo) (0x530B) - write only
dmac -> DMA Control (rw) (0x140B) = 0x00000000
dmaisa -> DMA Internal Start Address (rw) (0x150B) = 0x00000000
dmaesa -> DMA External Start Address (rw) (0x160B) = 0x00000000
dmaiea -> DMA Internal End Address (rw) (0x170B) = 0x00000000
dmacs -> DMA Channel Status (ro) (0x180B) = 0x00000000
dmacid -> DMA Context ID (rw) (0x1F0B) = 0x00000000
fcsepid -> FCSE PID (rw) (0x100D) = 0x00000000
cid -> Context ID (rw) (0x300D) = 0x00000000
urwtpid -> User R/W Thread & Process ID (rw) (0x500D) = 0x00000000
urotpid -> User RO Thread & Process ID (rw) (0x700D) = 0x00000000
potpid -> Priv. Only Thread & Process ID (rw) (0x900D) = 0x00000000
dmr -> Data Memory Remap (rw) (0x120F) = 0x01C97CC8
imr -> Instruction Memory Remap (rw) (0x320F) = 0x01C97CC8
dmamr -> DMA Memory Remap (rw) (0x520F) = 0x00000015
ppmr -> Peripheral Port Memory Remap (rw) (0x920F) = 0x40000015
pmc -> Performance Monitor Control (rw) (0x1C0F) = 0x00000000
ccnt -> Cycle Counter (rw) (0x3C0F) = 0x00000000
pmn0 -> Count 0 (rw) (0x5C0F) = 0x00000000
pmn1 -> Count 1 (rw) (0x7C0F) = 0x00000000
ddc -> Data Debug Cache (ro) (0x106F) = 0x0E00B240
idc -> Instruction Debug Cache (ro) (0x306F) = 0x00000000
dtrro -> Data Tag RAM Read Operation (wo) (0x126F) - write only
itrro -> Instr. Tag RAM Read Operation (wo) (0x326F) - write only
icdrro -> Instr. Cache Data RAM Read Op. (wo) (0x346F) - write only
dmtlbi -> Data MicroTLB Index (rw) (0x14AF) = 0x00000000
imtlbi -> Instruction MicroTLB Index (rw) (0x34AF) = 0x00000000
rmtlbe -> Read Main TLB Entry (wo) (0x54AF) - write only
wmtlbe -> Write Main TLB Entry (wo) (0x94AF) - write only
dmtlbva -> Data MicroTLB VA (ro) (0x15AF) = 0x80700200
imtlbva -> Instruction MicroTLB VA (ro) (0x35AF) = 0x8FF5A200
mtlbva -> Main TLB VA (rw) (0x55AF) = 0x00000000
dmtlbva -> Data MicroTLB PA (ro) (0x16AF) = 0x80700006
imtlbva -> Instruction MicroTLB PA (ro) (0x36AF) = 0x8FF5A026
mtlbva -> Main TLB PA (rw) (0x56AF) = 0x00000000
dmtlbva -> Data MicroTLB Attribute (ro) (0x17AF) = 0x00000003
imtlbva -> Instruction MicroTLB Attribute (ro) (0x37AF) = 0x0000000C
mtlbva -> Main TLB Attribute (rw) (0x57AF) = 0x00000000
cdc -> Cache Debug Control (rw) (0x10EF) = 0x00000007
tlbdc -> TLB Debug Control (rw) (0x11EF) = 0x00000000

Outcomes