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Problem in configuring USDHC-2 and USDHC-3 with different frequencies

Question asked by Asmita Amonkar on Dec 4, 2016
Latest reply on Dec 7, 2016 by Asmita Amonkar

Linux BSP version : 4.1
CPU : imx6 quad
Purpose: To configure the usdhc-2 with 48 Mhz and usdhc-3 with 42 Mhz


To obtain the change in frequencies following registers are configured:

1. PLL_PFD2 frequency is set to 339MHz: Configuration:
CCM_ANALOG_PFD_528n (Address: 0x20c8100)with divisor value : 0X1c1c19 (PFD2 divisor : 28) (528*18/28 = 339 Mhz)


2. CSCDR1(Address: 0x20c4024): 0x007E0B00; ( Changed usdhc3_podf divisor to 8, and usdhc2_podf divisor to 7)

3. CSCMR1(Address: 0x20c401C):0x00900000; (usdhc2_clk_sel set to 0 , usdhc2_clk_sel set to 0- selected derive clock from 396M PFD option)

4. CCM_CCGR6(Address: 0x20c4080)- value is set as 0xC30
5. CCM_CMEOR(Address: 0x20c4088)- value is 0x7FFFFFFF

With this configuration it was expected to change, usdhc-2 clock frequency to 48Mhz and usdhc-3 clock frequency to 42 Mhz. However, it was observed that usdhc-2 and usdhc-3 both clock frequencies are configured to 48 MHz.


It would be highly appreciated if any one can help understand the root cause of the problem or let me know if any of the configurations are missing.

Help needed urgently.