Archana Rao

MR2A16AMYS35 timing requirements

Discussion created by Archana Rao on Nov 30, 2016

Hi,

 

We are using MR2A16AMYS35 (NXP/freescale) MRAM in our design.

MRAM is being interfaced with OMAP TI processor.  

 

There is a parameter tWHAX (write recovery time) in write cycle 1(W_bar controlled) of MRAM.  This parameter is being referenced to address w.r.t. to Chip select (CS)/ Write enable (WE).

As per the processor, Address and Chip select (CS) have same cycle width.  We are facing tWHAX timing failure when CS is being measured against address since both have same cycle width.

 

Is it critical and necessary to meet tWHAX timing requirements?  Is it necessary to reference address against both CS and WE when verifying for tWHAX timing?

If not, in our case, can we measure address only against WE to meet tWHAX timing requirements?

 

Please advise.

 

Awaiting for your reply.

 

Regards,

Archana Rao

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