i.MX6 DDR Route Constraints Conflict

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i.MX6 DDR Route Constraints Conflict

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atillametetured
Contributor V

Hi

Below is taken from the i.MX6DQ6SDLHDG (Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors);

hwguideram.JPG

Below is taken from the HW_Design_Cheching_List_for_i.MX6DQP6DQ6SDL_Rev3.1.xlsx

excel.JPG

One says the constraint is <=25 while the other says +/-50 mils. Which one to trust? With one my design fails and the other it passes..

Regards,

Mete

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1 Solution
461 Views
art
NXP Employee
NXP Employee

Just follow the Hardware Development Guide document. Matching the control signals (CS, CKE, ODT) trace length within +/- 50mil margins is enough for normal operation.


Have a great day,
Artur

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2 Replies
462 Views
art
NXP Employee
NXP Employee

Just follow the Hardware Development Guide document. Matching the control signals (CS, CKE, ODT) trace length within +/- 50mil margins is enough for normal operation.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

461 Views
atillametetured
Contributor V

Hi Artur,

Thank you very much.

Regards,

Mete

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