AnsweredAssumed Answered

i.MX6 DDR Route Constraints Conflict

Question asked by Atilla Mete Turedi on Nov 30, 2016
Latest reply on Nov 30, 2016 by Atilla Mete Turedi

Hi

 

Below is taken from the i.MX6DQ6SDLHDG (Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors);

 

Below is taken from the HW_Design_Cheching_List_for_i.MX6DQP6DQ6SDL_Rev3.1.xlsx

 

 

One says the constraint is <=25 while the other says +/-50 mils. Which one to trust? With one my design fails and the other it passes..

 

Regards,

Mete

Outcomes