AnsweredAssumed Answered

no PST_CLK output in BDM mode

Question asked by Chang Liu on Nov 28, 2016
Latest reply on Dec 1, 2016 by Chang Liu

On my board, a MCF54415 is used in BDM mode. I am sure that JTAG_EN is low, RESET is high, Power is in the range of recommand value, clock is 50MHz, FB_CLK output in 62.5MHz. But no PST_CLK output and MCF54415 can't run in BDM mode with P&E MULTILINK. What factor can influence PST_CLK? Some error in BOOTMODE or BOOT Config can lead to that?