Hi,
We are now using I.MX6DQRM crystal for 24Mhz, we use the crystal frequency division to aud3, but we found that the frequency of aud3 is not what we want 44.1KHz, but 44.3khz, to solve this problem we find the relevant documents, the formula is:
PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
Also view the related clock generation Serial (cont):
Our kernel inside is the definition of the AUD3 output frequency dependent parameters(Annex for the complete documentation):
/* Let's initially set up CLKO with OSC24M, since this configuration is widely used by imx6q board designs to clock audio codec.*/
imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS_SRC],clk[IMX6QDL_CLK_OSC]);
imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4], 1179648000);
imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], 589824000); //johnli add 24576000X8=541900800
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI2_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI3_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI1_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_SSI2]);//johnli changed
/* Let's initially set up CLKO with OSC24M, since this configuration is widely used by imx6q board designs to clock audio codec.*/
//johnli changed clko from ssi2
// imx_clk_set_rate(clk[IMX6QDL_PLL4_BYPASS_SRC], 180633600); //johnli add 196608000X4=786432000imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS_SRC],clk[IMX6QDL_CLK_OSC]);
imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4], 1179648000);
imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], 589824000); //johnli add 24576000X8=541900800
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI2_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2], 24576000); //johnli add 48000X512=24576000 22579200
//add for ssi3
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI3_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI3], 24576000); //johnli add 48000X512=24576000 22579200
//add for ssi1
imx_clk_set_parent(clk[IMX6QDL_CLK_SSI1_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);//johnli add
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1_PRED], 147456000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1_PODF], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_rate(clk[IMX6QDL_CLK_SSI1], 24576000); //johnli add 48000X512=24576000 22579200
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_SSI2]);//johnli changed
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
Now we need to calculate or change the parameters to achieve the AUD3 output frequency of 44.1？
Best regards,
Xuemei Shao
Original Attachment has been moved to: clk-imx6q.c.zip
