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Writes to SSP1DR failing on SSP1

Question asked by Eddie Jakobitz on Nov 28, 2016

I am using an LPC2478 and it appears as though the SSP1 device does not function correctly.  I am attempting to use the SSP1 device in SPI mode as a SPI slave.  I have configured the device to work as a SPI slave and have connected the four SPI lines to a FTDI chip which is then connected via USB to a PC.  The FTDI chip acts as a SPI master and then sends data to the PC via USB.  Everything is working almost as expected.  I am able to send data in both directions and can see the data being sent and received correctly most of the time.  In fact, the data seems to transfer of over SPI correctly every time but once in every 32 to 64 bytes the transmit FIFO in the SSP1 device appears to be missing a byte that was sent to it and therefore also misses sending that byte over SPI and instead sends a later byte that should follow the bytes intended to be sent.  For example, if I am trying to write consecutive values such as 0x00 through 0x10 to the SSP1 transmit FIFO (SSP1DR), I occasionally see that one of the writes to SSP1DR fails.  In my interrupt service routine, I write values to SSP1DR until the bit is flipped that says the FIFO is full.  Usually I can write 8 bytes and then the FIFO says that it is full.  When that happens I get bytes 0x00 through 0x07 sent to the master.  But sometimes the code does 9 writes to the FIFO before the FIFO says it's full.  And it appears that one of the writes to SSP1DR failed which is why the 9th write is required in order to fill the FIFO.  When that happens, the master receives 0x00, 0x01, 0x02, 0x04, 0x05, 0x06, 0x07, 0x08.  As you can see, 8 bytes get transferred but the value 0x03 appears to have never gotten put into the FIFO and instead an extra write to the FIFO added 0x08 which does get transferred.  In short, it appears that writes to SSP1DR occasionally fail.  The FIFO correctly reports that it is not full until 8 bytes get written to it but sometimes it requires 9 writes to fill the FIFO because one of the writes failed.  The SPI transmissions always seem to work but the population of the transmit FIFO does not always work correctly.  I have attached the code module that includes the SPI setup and the interrupt service routine as well as the other SPI related routines.   Any help would be much appreciated.  Also, I can add any further detail if I have left out any important points.  

Original Attachment has been moved to: SPISlaveSupport.c.zip

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