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TDM UMCC synchronization in transparent mode

Question asked by Sebastien G on Nov 28, 2016
Latest reply on Dec 12, 2016 by Pavel Chubakov

Hello,

 

We are currently writing a driver to operate a T1040 QuiccEngine TDM link with UMCC feature.

This link is supposed to work in transparent mode, and we do not need to use any synchronization pattern.

We have first tried to deactivate the synchronization by setting CHAMR[SYNC] = 0 but the received data are shifted. This is specified in MCC 23.2.2.2 chapter of the QEIWRM. Even if related to the MCC, I suppose this restriction is also applicable to the UMCC.

 

ZDSTATE register description

We have also tried to configure an 8-bit synchronization pattern which works fine for 8-bit time slots, but data in 16-bit time slots is always shifted, even with a 16-bit pattern.

 

The picture above seems to show a configuration where no pattern is used and data is not shifted (note 3) but the RCVSYNC and ZDSTATE informations are missing...

 

Could someone please provide us with the missing configuration?

 

Many thanks,

Sébastien

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