We are encountering an issue with the calibration of ADC peripheral (Kinetis MK10DX128VLH5).
On some PCBA, we figured out that a cold start (regarding power supply) leads to ADC conversion errors (around 3%)
After investigation, it seems that the issue comes from ADC calibration.
With a hot start, there is no conversion error è Calibration is OK
With a cold start, conversion error is around 3% è Calibration seems to be inaccurate
- Hot start = VCC is removed and put again while UART is connected to computer
- Cold start = VCC is removed and put again while UART is not connected to computer
Gain and offset calibration data have been logged and compared.
Hot start :
PG=0x81B1 = 1.013214111
Conversion Result = 3696
Cold start :
PG=0x823E = 1.01751709
Conversion Result = 3814
Error (Conversion Result) = (3814/3696-1)x100 = 3.2%
Ratio (Gain calibration data) = (1.0175/1.0132-1)x100 = 0.42%
Gain calibration data are very close but conversion results are farther. Is it the right calculation ?
- VREF peripheral is initialized and enabled
- Wait that VREFST flag is set in VREF_SC register
- Initialize ADC peripheral
- Start ADC calibration
We have noticed that waiting a few time between VREFST is set and start of calibration solves the issue.
So, we wonder if calibration is impacted by VREF peripheral and if it is recommended to wait some time before starting calibration.
Calibration is not done in the conditions mentioned in the reference manual.
Calibration is done with an ADC clock of 10Mhz, no averaging and VCC is rising.
VREF_SC = 0xE1 = VREF_SC_VREFEN_MASK | VREF_SC_REGEN_MASK | VREF_SC_ICOMPEN_MASK | VREF_SC_MODE_LV(1)
ADC0_CFG1 = 0x00000094 = ADC_CFG1_ADLPC(1) | ADC_CFG1_ADIV(0) | ADC_CFG1_ADLSMP(1) | ADC_CFG1_MODE(1) | ADC_CFG1_ADICLK(0);
ADC0_CFG2 = 0x00000000 = ADC_CFG2_ADLSTS(0);
ADC0_SC2 = 0x00000001 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG(0);
ADC0_SC3 = 0x00000000 = ADC_SC3_ADCO(0) | ADC_SC3_AVG(0);
Regarding VREF, there is something strange.
In the reference manual, it’s written:
In the datasheet, tstup is given for a maximum of 100µs.
As you can see it on the following screenshot, VREFST flag takes about 6µs to be set (after VREF startup) and VREF_OUT takes more than tstup (100µs) to be stable.
So, we wonder why VREF_OUT takes more than 100µs to be stable and if it may have a link with our calibration issue.
In the reference manual, it is written that ADC used VREF_OUT as reference and not internal bandgap voltage.
So, if we start ADC calibration just after VREFST is set, VREF_OUT is still not stable and calibration is done with a reference that is not stable.
On some other PCBA, calibration works well whereas VREF_OUT has the same behavior.
Can you help us to understand these issues ?
Thanks in advance,