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Bus contention on LPC43xx

Question asked by Daniel Goertzen on Nov 24, 2016
Latest reply on Nov 30, 2016 by Daniel Goertzen

I am trying to understand if 2 (or more) bus masters can *simultaneously* move data through the bus matrix as long as they are talking to different slaves.

 

My scenario is GPDMA moving data from SGPIO to a RAM buffer while USB0 moves another RAM buffer onto the wire.  My concern is that bus contention might make the DMA transfer take too long and lose data.  Can I avoid bus contention by assuring that the RAM buffers are on different SRAMs?

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