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Long time LPC2k user getting started with LPC4337

Question asked by Baldur Gislason on Nov 25, 2016
Latest reply on Dec 29, 2016 by Baldur Gislason

Hello, long time (10+ years) user of LPC2100 and LPC2300 series here, and I'm starting a new project based on the LPC4300 series. Currently using a dev board with LPC4337 LQFP144 chip which I've set up my build environment for, written boot code and linker script and have it running code on single core now with interrupts.

I have some concerns which I haven't found answered in any of the documentation I've read so far.

 

One, for the time being I'm using Flash Magic until I've managed to port my custom boot loader to this platform, and Flash Magic for some dumb reason has an option to select which flash bank to write to. This is very counter intuitive as the hex file specifies where to place each and every byte it contains. Am I right in thinking this option has no effect whatsoever unless I have Flash Magic generate the boot vector checksum for me, in which case this option tells it where to place the checksum?

 

Two, what is the expected flash fetch time when the flash accelerator misses?

 

Three, with the two flash banks (A/B) being separated as they are, is one bank available for access during erase operations on the other bank?

 

Four, implementation wise, what is the bandwidth of the AHB layer? How does it cope with two cores running at the same time? Are the cores able to run at full speed as long as they're not accessing the same flash banks and same RAM banks? Does switching on the M0 core automatically have any implicit performance effect on the M4 core?

 

Five, does the LPC4337 or does it not provide the USB ROM API? User manual states "The USB ROM API is available on parts LPC4350/30/20 and LPC43S50/S30/S20." and does not include the 4337 in that list. However the sample code provided in lpc4337.zip distributed with the LPCxpresso IDE has examples using the USB ROM API.

 

Six, since the Cortex M4 does not provide two separate interrupt channels, IRQ and FIQ, I may need to use nested interrupts in my application. On the LPC2000 series I managed to avoid interrupt nesting by using the FIQ to handle the one interrupt that was jitter sensitive. Are there any code examples available showing the use of nested interrupts on the LPC4000/Cortex M4 platform?

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