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Unused SNVS_TAMPER pins of IMX6UL

Question asked by Uma Sundaram on Nov 24, 2016
Latest reply on Nov 24, 2016 by Yuri Muhin

Hello,

 We are designing a PCB with IMX6UL processor(Part No: MCIMX6G2DVM05AA).

   According to TAMPER_PIN_DISABLE[1:0] ,the pins can either be enabled for tamper detection or used as GPIO.

(Please find the following configuration  as on Pg214 of IMX6UL reference manual.)

 

Also page 131 of IMX6UL datasheet specifies that 1M to be added in the following conditions.

1.When the tamper pins are configured as GPIOs

2.When the pins are enabled for tamper detection.

 

 

Q1:  Does the above reference means that 1M resistor be added to the SNVS_TAMPER pins, on all the above cases.

            

Also can you please clarify the handling of SNVS_TAMPER pins in the design, for the following conditions.

Q2.The SNVS tamper pins are not used either as GPIOs  or for tamper detection function.

Does all the 10 pins (SNVS_TAMPER[0:9]) require 1M resistor to GND(or pulled up to SNVS).

Can the pins be left floating ?

 

Q3.Only certain tamper pins are configured as GPIOs(as specified by the bits in TAMPER_PIN_DISABLE[1:0]) in SNVS_TAMPER[0:9].Can 1M pull down/pull up resistors be added only for them.

 

 

 

 

Thanks in anticipation.

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