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i.MX7D power down sequencing in different scenarios

Question asked by sebastianrespondek on Nov 23, 2016
Latest reply on Nov 29, 2016 by Yuri Muhin

Hello,

i am working on a design using i.MX7D using the PF3000 (without LICELL), and i am trying to figure out how to handle the power-down sequencing. I would appreciate your help regarding the following questions:

 

  1.  What should be done to make shure the reccomended power down sequence of the IMX7D works as described in the datasheet?
  2. Do i have to assert a reset on i.MX7D before a Power-Down? What would be the consequences if this is not done?
  3. What would be the consequences if the power-down-sequencing is not done as described in the IMX7DCEC datasheet (p.39/40) (i.e. VREF_DRAM is turned off after VDD_SOC, or V_SNVS is turned off before the other voltages)?
  4. In Case of a Board-Power-Supply-Faillure the PMIC Input Voltage would be removed. How could damage of the i.MX7D be prevented in such a case?
  5. Could the ONOFF-Pin (via INTB from PMIC) be used to turn the i.MX7 off in case of the power supply faillure described above? If not, which pin should be used/ connected to INTB?

 

Thank you very much in advance for your help!

 

Best regards,

Sebastian

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