Q1:To the CMPU, what is the “instruction memory” and what is “data memory”
Q2: according to Q1, there are 3 types of region descriptor. I wonder are the following configurations right?
For 6 instruction memory regions: INST = 1; SHD = 0; ESEL = 0/1/2/3/4/5
For 12 data memory regions: INST = 0; SHD = 0; ESEL = 0/1/2/3/4/5……11
For 6 instruction or data memory regions: INST = 0/1; SHD = 1; ESEL = 0/1/2/3/4/5 (INST=0 means this is data memory entry while INST=1 means this is instruction memory entry)
Q3: in the pic above, when SHD = 0, it says ” The shared portion of the region descriptor table is not accessed on a mpure or mpuwe operation”-------what does this mean?
Q4: the CMPU MAS0 register(pic below), it mentioned about “Cache Inhibit & Guarded”, I would like to know under what circumstances I should enable Cache Inhibit & Guarded? What does “Guarded” mean? Is there any advice or documents for this?
Q5: In the pic above, what does the “GOVR” mean? What will happen if “this entry” and “other matching entry” both have GOVR=1(while G is opposite), who will override who?
Q6: Does “ BYPSR = 1 ”(pic below)mean if the cpu is in supervisor mode, the cpu can read any memory no matter how the entry setting? (except the CI&G setting, they still work)
Q7: what will happen if the access violate the setting of the entry? Generate data storage interrupt & instruction storage interrupt?
Q8: what will happen if there is a conflict between CMPU and SMPU?
Q9: when the pid0 == tid, does that mean the process must obey the limit of this entry? In another word when a process whose pid is different from all the 24 entry’s tids, this process will have no limitation of access the memory?
Q10: I write a simple program about writing CMPU entry. I wonder is this way right?
It seems the “mpuwe” doesn’t work? How use the “mpuwe,mpure,mpusync” instructions?
Can Lauterbach debugger display the CMPU register and how?
Thank you very much!