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Any setting of PCIe is different between i.MX6Q and i.MX6Solo?

Question asked by Oliver Kuo on Nov 21, 2016
Latest reply on Nov 21, 2016 by Yuri Muhin

Hi,

 

We have a custom board with i.MX6Q/Solo.

The PCB is same and may mount i.MX6Quad or i.MX6Solo, the BSP is L3.0.35_4.1.0.

The mPCIe wifi card, Unex DNXA-116 using Atheros AR9386, works properly without issues on i.MX6Solo, but would caused system halt on i.MX6Quad.

There was no error message posted out when system halted, it was just sudden death.

3 pieces of i.MX6Quad halted on differnt point, one board could play video for awhile and then halted, another halted when executed lspci or loaded ath9k.ko and the other halted while booting, the symptom is variously.

If I defined CONFIG_IMX_PCIE_RC_MODE_IN_EP_RC_SYS, system was stable but mPCIe wifi card couldn't be detected.

So, any setting for mPCIe is different between i.MX6Q and Solo?

 

static int _clk_pcie_enable(struct clk *clk)
{
   unsigned int reg;

#ifndef CONFIG_IMX_PCIE_RC_MODE_IN_EP_RC_SYS
   /* Activate LVDS CLK1 (the MiniPCIe slot clock input) */
   reg = __raw_readl(ANADIG_MISC1_REG);
   reg &= ~ANATOP_LVDS_CLK1_IBEN_MASK;
   __raw_writel(reg, ANADIG_MISC1_REG);

   reg = __raw_readl(ANADIG_MISC1_REG);
   reg |= ANATOP_LVDS_CLK1_SRC_SATA;
   __raw_writel(reg, ANADIG_MISC1_REG);

   reg = __raw_readl(ANADIG_MISC1_REG);
   reg |= ANATOP_LVDS_CLK1_OBEN_MASK;
   __raw_writel(reg, ANADIG_MISC1_REG);
#endif

   /* Enable PCIE ref clock */
   reg = __raw_readl(PLL8_ENET_BASE_ADDR);
   reg |= ANADIG_PLL_ENET_EN_PCIE;
   __raw_writel(reg, PLL8_ENET_BASE_ADDR);

   _clk_enable(clk);

   return 0;

 

Any suggestion would be appreciated.

 

Best regards,

Oliver

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