AnsweredAssumed Answered

i.MX6SX can not get into the steady link state with x86

Question asked by zengxing yuan on Nov 20, 2016
Latest reply on Nov 21, 2016 by zengxing yuan



Hereafter we ourself are debugging the issues about pcie between imx6sx and x86, after configuring the pcie clock, device type(EP mode) and inbound in imx6sx, data can be accessed into imx6sx from x86, however, it is extremely not stable. Sometimes the data can be written into the ddr of imx6sx from x86, sometimes NOT. Is there anybody run into this problem?


I have written the command to check the PCIE_PHY_DEBUG_R1 register, find that the pcie link state is changing over time, sometime it is in link up state, sometime it is link down or in training state with x86.