I am using the T1042 in one of my designs. I intend on using the first 3 serdes SD1[0-2] for 1G serdes and the remianing 4 SD1[3:7] as Pcie gen2. I would like to know if this configuration is possible. Next is what are the clock requirements for the same? Also can you guide me with what configuration changes need to be made to accommodate this particular configuration.