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What is the correct Read/Write timing sequence on the MC68332?

Question asked by Chet Kaufman Employee on Nov 15, 2016
Latest reply on Nov 28, 2016 by TomE

From my customer:

Question: Is the R/W# signal guaranteed to be held low through all of S5 during a write cycle? Section 5.4.2 "Write Cycles" in the MC68332 SIM (System Integration Module) Reference Manual gives a description of a write operation. Figure 5-5 shows the logic levels of various control signals through states (S0 - S5) of a write cycle. The description says "R/W# remains valid throughout S5", and Figure 5-5 also indicates this. However, Figure A-5 and Table A-6 in Appendix A give detailed timing information for the R/W# signal during a write cycle. Timing specfication #17 (tSNRN) states "AS#, DS#, CS# Negated to R/W# High" is a minimum of 15ns. I interpret this to mean that R/W# could transition low-to-high as soon as 15ns after CS# is negated. CS# is negated at the end of S4/beginning of S5. Specification #12 (tCLSN) states CS# can take 2 to 29 ns to negate after the clock goes low at the end of S4. Combining spec #17 and #12, this means the R/W# signal could go low-to-high as soon as 17ns after the beginning of S5. For a 16MHz system clock (62.5ns period, 31.25ns half-period), this means R/W# could transition high about halfway through S5. Thus, there is a contradiction between what is stated in Section 5.4.2 and the timing specifications given in Table A-6 of Appendix A. Should I go with what Section 5.4.2 says or with what Table A-6 says? Am I interpreting the spec in Table A-6 correctly? Again, my ultimate question is: Will R/W# be held low throughout the state S5 during a write cycle? Reason for question: I am asking because we are replacing obsolete 5V Flash memory on a 20 year old product with new 3.3V Flash. We are adding a level shifting transceiver to shift data signals between 5V and 3.3V to accommodate this "new" Flash. I would like to use the R/W# signal to control the direction of this transceiver, but if R/W# is not held low all the way to the end of a write cycle (i.e. through the end of S5), it will cause bus contention problems and I will need to use something else in the design. This is still in the design phase so we have no measurements to take. However, I could go in and take measurements on the old product as you suggested. Our full part number is MC68332ACEH25. The SIM manual I am referencing is located here: http://www.nxp.com/files/microcontrollers/doc/ref_manual/SIMRM.pdf?fasp=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf

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