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MPC5604E Clock Architecture Issues

Question asked by Suhas S on Nov 14, 2016
Latest reply on Nov 15, 2016 by Lukas Zadrapa

Hi,

I'm working on MPC5604E, and wanted to get clock out of "clk_out" pin [PCR36, Pin No. 62], according to Clock Architecture Block diagram [Refer "Img1"], Input to the "clk_out" pad is from FMPLL_0 after FMPLL_CLK_DIV, But according to over experimentation its not the case, according to what I have validated the input to "clk_out" is from FMPLL_0 before FMPLL_CLK_DIV. It also says maximum frequency supported on "clk_out" pad is 32MHz [Refer Img2]

but we have tested it upto 120MHz. Do clarify the issues.

 

 

Thanks & Regards 

SUHAS S

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