I'm actually getting started with all the things, chances are the problem I describe here is just misinterpretations of my part.
I have a KL17 chip soldered in a breakout board. After powering the chip and connecting UART I'm able to communicate and retrieve data using the ROM bootloader.
I'm about to try flashing a compiled code the first time. I don't decided yet for a programmer/debugger (which one to buy/what's best for me), and actually trying the bootloader for the usual tasks. This way I'm taking care of revising aspects that could lock me out from bootloader access (like BOOTSRC_SEL bits on FTFA_FOPT), and other details.
For what I see KDS (using Processor Expert/SDK 1.3), compiles for the entire flash image, including flash configuration field and everything.
After compiling, the flash configuration field ends as "FF FF FF FF FF FF FF FF FF FF FF FF FE 3F FF FF". I opened the resulting .bin in a hex editor to retrieve this. "3F" being the FTFA_FOPT definitions.
In the project I edit the fsl_clock_manager component and set Core Clock Prescaler to 2, that's the value of OUTDIV1.
After hitting "Generate Processor Expert Code" and "Build Project" int the resulting .bin file the configuration field is show exactly as before for LPBOOT bits, that's, the same 3F value.
Reading the user guide my understanding is that chip will always read FTFA_FOPT registers for the defined fields. I was expecting to see this change on the configuration field. Actually trying to understand how it works my question is: Why changes aren't being reflected? There's something/set that takes priority over the settings defined in the FOPT fields?