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Question about Sensor Interface Timing in i.MX6S

Question asked by ko-hey on Nov 10, 2016
Latest reply on Dec 5, 2016 by ko-hey

Hi all

 

I have a question about Sensor Interface Timings.

Especially, Gated Clock Mode and Non-Gated Clock Mode.

 

Q1.

Is the data latched at the rising edge of the valid pixel clock ?

 

In  IMX6SDLIEC Rev. 7, 10/2016 , there are following description for Sensor Interface Timing in Gated Clock Mode.

"Data is latched at the rising edge of the valid pixel clocks."

 

However, it looks the data is latched at falling edge in the Figure 58 of  IMX6SDLIEC Rev. 7, 10/2016.

 

Which is correct ?

 

Q2.

Is the data latched at the rising edge of the valid pixel clock ?

 

In  IMX6SDLIEC Rev. 7, 10/2016 , there are following description for Sensor Interface Timing in Non-Gated Clock Mode.

"The timing is the same as the gated-clock mode”

 

However, in the Figure 38-17 and Figure 38-18 of RM, the edge is the oppsite.

 

 

Is the data latched at the rising edge of the valid pixel clock in Non-Gated Clock Mode ?

 

 

Ko-hey

 

 

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