MPC5668 ......not able to access DSPI_C registers....

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MPC5668 ......not able to access DSPI_C registers....

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stefintomy
Contributor I

Please help me to sort out this issue....how can i  enable bridge A

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davidtosenovjan
NXP TechSupport
NXP TechSupport

We have been using following MMU setting in Lauterbach:

;MMUSCR0: enable address translation bypass

Data.Set SPR:0x3F4 %LONG 0x80000000

;set up TLBs

MMU.TLB1.SET 0. 0xC0000500 0xFFF0002A 0xFFF0003F ;peripherals and boot rom

MMU.TLB1.SET 1. 0xC0000900 0x00000020 0x0000003F ;FLASH

MMU.TLB1.SET 2. 0xC0000900 0x20000020 0x2000003F ;external SRAM

MMU.TLB1.SET 3. 0xC0000500 0x40000028 0x4000003F ;internal SRAM

MMU.TLB1.SET 4. 0xC0000500 0xC3F00008 0xC3F0003F ;AIPS_A

 

In Codewarrior is configure in INIT_Derivative function.

 

AIPS_A must be initialized:

 

/* Write one MMU Table Entry:               */

/* r3, r4, r5 and r6 must hold              */

/* the values of MAS0, MAS1, MAS2 and MAS3  */

asm void InitAIPS_A( void )

{

    nofralloc

 

    mflr     r29                         /* Save off return address in NV reg */

   

    // MMU.TLB1.SET 4. 0xC0000500 0xC3F00008 0xC3F0003F ;AIPS_A

   

    #define MAS0_AIPS_A 0x10040000

    #define MAS1_AIPS_A 0xC0000500

    #define MAS2_AIPS_A 0xC3F00008

    #define MAS3_AIPS_A 0xC3F0003F

    e_lis   r3, MAS0_AIPS_A@h

    e_or2i  r3, MAS0_AIPS_A@l   

    e_lis   r4, MAS1_AIPS_A@h

    e_or2i  r4, MAS1_AIPS_A@l   

    e_lis   r5, MAS2_AIPS_A@h

    e_or2i  r5, MAS2_AIPS_A@l

    e_lis   r6, MAS3_AIPS_A@h

    e_or2i  r6, MAS3_AIPS_A@l       

    msync

    se_isync        

    bl  WriteMMUTableEntry

    se_isync

 

    mtlr    r29

 

    blr

}

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