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How to Set and Reset I2C_LOCKED bit in NS_REG register inside Session Register, from I2C interface

Question asked by KF Choong on Nov 9, 2016
Latest reply on Jan 4, 2017 by KF Choong

Hi Sir / Madam,

I encounter communication problem when NXP NTAG 1K communicate with peer NFC device.

My problem is I am not able to Set or Reset I2C_LOCKED bit in NS_REG register inside Session Register. From datasheet (NT3H1101/NT3H1201.pdf, page 27/65, Table 14), this bit can be Read and Write by I2C interface.

 

During peer NFC device(RF interface) has read the mirror SRAM in NXP NTAG 1K, NS_REG = 0xA9 or 0x29, NC_REG=0x7E.  For NS_REG = 0xA9, it means NDEF_DATA_READ = 1b, RF_LOCKED = 1b, SRAM_RF_READY=1b and RF_FIELD_PRESENT=1b. I can understand SRAM_RF_READY=1b because RF interface is read from Mirror SRAM, Not Mapped SRAM.  But, may I know why Memory is still lock to RF, as shown in RF_LOCKED = 1b ?  Doesn't it will change to RF_LOCKED = 0b and I2C_LOCKED = 1b ? Because RF interface has read the last page of Mirror SRAM Block, as this is correctly shown in NDEF_DATA_READ = 1b. 

 

Is the above phenomena also caused by RF interface reading from Mirror SRAM, NOT Mapped SRAM ?  Then, may I know after RF interface has read the Mirrored SRAM, how I2C interface able to write data again ?

 

As an attempt to solve above problem, I have try to manually write 1b to I2C_LOCKED.  But I am not able to write on this bit although datasheet mention that this bit is R&W from I2 interface.

 

During this experiment and observation, RF field is stable and constantly provided. In addition, Pass through and its direction is maintained as shown in NC_REG=0x7E reading.  Also, RF is successfully reading on the correctly configure SRAM MIRROR BLOCK address. 

 

 

Please advice soon.

 

 

Thank you very much for your help and advice.

 

 

Cheers,

KF Choong

Skype: ohchat12

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