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Question, clock tree for i.MX6SoloLite UART

Question asked by AVNET JAPAN FAE (team share account) on Nov 6, 2016
Latest reply on Nov 21, 2016 by AVNET JAPAN FAE (team share account)
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Dear team,

 

I would like to ask about clock tree for UART of i.MX6SoloLite.

My customer wants to use osc_clk as a source clock of UART for their board.

They do not want to use PLL for the source clock because the PLL setting has to be changed frequently to ‘bypass’.

According to i.MX6SL reference manual, the clock tree is as below.

 

They want to configure UART operation with over 1Mbps bitrate.

And they believe that it is possible when they set a divider into 1/16.(24MHz/16=1.5M)

But after they verified actual behavior of the UART, they believe that the 1/6 divider is added as below.

The UART bitrate on their board was lower than the expected value.

Is it true?

Could you show me what they should do to achieve 1MHz bitrate of UART with the source clock of osc_clk?

 

Thanks,

Miyamoto

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