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MPC8250 timing issue with SDRAM

Question asked by John Man on Nov 2, 2016
Latest reply on Nov 10, 2016 by John Man


I meet a problem regarding the timing between MPC8250 and SDRAM.

The data retention period(after rising clock edge to data invalid) from MPC8250 is 0.5ns min. (SP30), However, SDRAM requires hold time after rising edge 0.8ns (tAH or tDH). 


But in MPC8250 datasheet, it says it can achieve glueless interface to SDRAM memory. Could you help to explain how MPC8250 can mitigate this timing gap?