In our design, we have given a solution based on i.MX6q with 2 GB DDR3 interfaced to MMDC's CS1, without CS0.
As per NXP support team, this method of mounting DDR on CS1 without CS0 is not recommended.
But we still explored options to booting using the above configuration and able to boot the Bootloader with below modifications to the DDR configuration and Bootloader code:
- Enabled both CS0 and CS1 chip selects with address mirroring enabled.
- CS0 address space is set from 0x10000000 to 0x50000000 (1GB).
- CS1 address space is set from 0x50000000 to 0x90000000 (1GB).
- Bootloader is built to execute from CS1 address space.
We are not able to extend the CS0 and CS1 address space to 2GB boundary (CS0:0x10000000 to 0x90000000. CS1:0x90000000 to end of memory). With this configuration Bootloader doesn't boot from CS1.
Can someone give more information on what is actually happening when we set the MMDC controller with above configuration?
And also we are not able to boot Linux, although we changed the address in Makefile.boot. Are there any other Linux BSP changes to be done?
Thanks and Regards,