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About ddr frequency change

Question asked by Masaki Hayakawa on Oct 31, 2016
Latest reply on Nov 3, 2016 by Masaki Hayakawa



Android version is ICS, NXP patch name is imx-android-13.4.1.

Target platform is custom board of epdc system on i.MX6DualLite.

The configuration is two Micro 1GBx32 LPDDR2 in a dual-channel interleaved, 64-bit wide memory system.


We donwloaded patch files on the following site, files are 0001-Support-LPDDR2-on-6DL-platform_Uboot and 0001-Support-LPDDR2-on-6DL-platform_Kernel, and applied.


But after lpddr2 frequency change from 24MHz to 400MHz, kernel frequenctly freeze with dump messages.


We removed CON_REQ bit control of MMDCx_MDSCR register when lpddr2 frequency change entry and ext  (file:arch/arm/mach-mx6/mx6_lpddr_freq.S), and it appears to be stable.

We refered to fsl-yocto-L4.1.15_1.2.0-ga.


Please tell me whether CON_REQ bit control of MMDCx_MDSCR register is need or not.

We think that this control is need...  why did you remove this control on fsl-yocto-L4.1.15_1.2.0-ga ?


Best Regards.

Masaki Hayakawa