I'm little bit confused about how COP watchdog behave in VLPS mode on KL chips (KL16Z in my case).
Accroding to reference manual, the COP couter is zeroed but no hint given about that it is counting or not when clocking is configured to run from 1kHz LPO (since LPO is running in VLPS). Will the COP count (or invoke chip reset) after at most 1024ms spent in VLPS or it will not? Thanks!
If the 1 kHz clock source is selected, the COP counter is re-initialized to 0 upon entry to either Debug mode or Stop (including VLPS or LLS) mode. The counter begins from 0 upon exit from Debug mode or Stop mode.