1. Processor Expert in KDS, 3.2.0 as the basis of my project
2. Processor is MKV31F512VLL12
3. Have working compiles and debug using the a tower board JTAG interface from it (PNE debugger)
4. Have struggled mightily with PE and these trigger sources to run the ADC samples, though found most problems so far...
Problems somewhat resolved:
1. In the ADC_LDD bean, modifying the Trigger options does not generate any code.
2. To solve #1, the SIM bean must be added to the project, and the settings for ADC settings (SIM_SOPT7) must be manually set. At this point, the Trigger options become "intelligent", and the SIM_SOPT7 register then gets set properly.
3. The Conversion Time dialog of ADC_LDD presents a list of available timings, some of which (unknown to me when I started) are not available in the clock mode I am setting the bean up for, such as ALT_CLK2. It is very easy to select a timing clock that is not even on, leaving the ADC core non-clocked. You have to make dang sure you select an available clock here, and not leave it on Automatic. Otherwise you will spend days blaming the trigger signals like I did.
I have a project put together where I have been able to do the following:
1. Take simultaneous 2x ADC conversions triggered and based upon the PIT module channels for trigger. To do this I had to resolve the above problems.
2. I have DMA working just fine (Beans here rock!) took me all of about 10 minutes to add DMA support vs. single-sample interrupts and manual copy to buffers.
3. Many other peripherals and timers working just fine within the project.
4. I added a new Init_PDB bean to my project to start using the PDB (Programmable Delay Block) for my trigger source rather than PIT to get access to delays in trigger abilities.
5. I followed this example: http://cache.nxp.com/files/32bit/doc/app_note/AN4688.pdf?fpsp=1&WT_TYPE=Application%20Notes&WT_VENDOR=FREESCALE&WT_FILE_… to try and replicate the settings as best I could on the PDB.
5. I can get the PDB to provide regular interrupts to a custom interrupt vector and increment a counter at my expected interval, so I know PDB is enabled, interrupts are on, working and setup.
What I cannot do:
1. I cannot get the PDB to trigger ADC conversions. I simply change SIM_SOPT7 register from the existing (and working) PIT timer to the PDB timer (only on one of the two channels), and the ADC channel 0 trigger source settings. After mapping to the new trigger source, the ADC channel no longer triggers, even though I continue to get regular PDB interrupts. SIM_SOPT7 is 0x8500 (First byte 0x85 says alternate trigger: PIT, second byte of 0x00 is default PDB trigger).
2. I have also tried the FTM modules in the past with the same problem, I cannot get them to trigger the ADC. I cannot trigger the ADCs with anything but the PIT timer it seems.
I have run out of ideas other than to blame a problem with the core of the CPU, or some errata I don't know about that is blocking me. I would expect the PDB to function for triggers as that is supposed to be the default trigger routing after reset.
I have attached the Processor Expert file in hopes that someone can poke around the PDB settings or SIM settings to see if I am simply missing something critical to get the ADCs to trigger from the PDB.
Thank you for any help!
Original Attachment has been moved to: ProcessorExpert.zip