AnsweredAssumed Answered

Question, i.MX28 hardware design

Question asked by AVNET JAPAN FAE (team share account) on Oct 26, 2016
Latest reply on Oct 31, 2016 by Artur Petukhov

Dear team,

 

I would like to ask about the hardware design of i.MX28 board.

My customer is in HW design phase for their own new i.MX28 board, and they have some questions.

Please give your answers to the following questions.

(1)

They want to supply power to ETHER-PHY from VDDIO for their new board. And they already confirmed that the max power consumption for VDDIO is OK. But HW design checklist(i.MX28_HW_DESIGN_CHECKLIST_v1.3.xlsx) says that “The Ethernet PHY cannot be powered by VDDIO.”.

Could you show me why Ether-PHY cannot be powered by VDDIO?

Is it really impossible?

(2)

For their design, the power of i.MX28 is fed from only VDD5V.

In such condition, the customer thinks there is no need to connect any capacitors to DCDC_BATT pin of i.MX28.

Is it true?

(3)

For their design, VDD1P5 of i.MX28 does not feed anything.

In the above condition, they think that there is no need to add capacitors to VDD1P5 pin.

Is it true?

(4)

In the HW design checklist of i.MX28, the following statement is written for the spec of crystal.

“ESR < 50 ohm”

Can I understand that the ESR of crystal should be lower than 50 ohm?

(5)

In the schematic of i.MX28-EVK, the following statement is written as for the routing of EMI_DDR_OPEN - EMI_DDR_OPEN_FB.

“ Short to match trace length to CLK+DATA signals”

Can I understand that the meaning of the statement is as below?

The trace length between EMI_DDR_OPEN and EMI_DDR_OPEN_FB should be same as twice of the length of CLK(or DATA) signal?

They found that the signal lines on EVK are like above.

If there are any documents for the detailed information on this, please let me know.

 

Thanks in advance.

Miyamoto

Outcomes